The present invention generally relates to a phase shift circuit, and more particularly to a phase shift circuit suitable for a repeater in an optical communication system, such as an optical submarine (underwater) repeater. Further, the present invention is concerned with a repeater using such a phase shift circuit.
Phase shift circuits are widely used in various fields. A repeater in a communication system has the functions of retiming, reshaping and regenerating, and includes a phase shift circuit. Referring to FIG. 1, there is illustrated a conventional repeater used, for example, in an optical submarine communication system. An optical data signal on a transmission line is input to a opto/electric converter 1, which includes an avalanche photodiode. The opto/electric converter 1 converts the optical data signal into an electrical data signal. An equalizing amplifier 2 amplifies the electrical data signal from the opto/electric converter 1 and outputs an amplified data signal, which is applied to a decision circuit 3 and a timing extracting circuit 4. The timing extraction circuit 4 derives a clock signal from the amplified data signal supplied from the equalizing amplifier 2. The decision circuit 3 determines whether transmitted data is "1" or "0" in accordance with the clock signal from the timing extraction circuit 4. Then, an output data signal is supplied to an electrooptical converter (not shown).
As shown in FIG. 2, the decision circuit 3 makes a decision in the signal from the equalizing amplifier 2 at a timing of each rise of the clock signal from the timing extraction circuit 4. Thus, it is required that peaks of the waveform of the signal from the equalizing amplifier 2 coincide with the rises of the clock signal. For this requirement, it is necessary to adjust the phase of the clock signal.
Referring to FIG. 3, there is illustrated a conventional phase shifter for adjusting the phase of the clock signal from the timing extraction circuit 4. The phase shifter shown in FIG. 3 is a coaxial cable line 5, which is connected between the timing extraction circuit 4 and the decision circuit 3. The length of the coaxial cable line 5 is adjusted so that the rises of the clock signal coincide with the peaks of the waveform of the signal from the equalizing amplifier 2.
Another conventional phase shifter is illustrated in FIG. 4 (see Japanese Laid-Open Patent Application No. 54-102855). The phase shifter shown in FIG. 4 is composed of a resonance circuit 6 and an LC phase shifter 7. The phase of the clock signal applied to the resonance circuit 6 is adjusted by varying resistance of a resistor R or capacitance of capacitor C.
However, the use of the coaxial cable line 5 shown in FIG. 3 encounters a troublesome adjustment, and occupies a large mounting area. Additionally, it is difficult to arrange the coaxial cable line 5 together with other elements on an integrated circuit (IC) chip.
The configuration shown in FIG. 4 has the following disadvantages. It is difficult to provide the resistor R and the capacitor C on an IC chip and adjust resistance of the resistor R or capacitance of the capacitor C formed on the IC chip. Further, the signal from the resonance circuit 6 has a very small amplitude and is thus affected by noise. Generally the resistor R and the capacitor C are externally attached to the IC chip. The failure rate increases with an increase in the number of structural elements. The use of elements to be externally attached to the IC chip leads to an increased number of structural elements, which provides an increased failure rate. Moreover, it is difficult to adjust the phase of the clock signal when it has a high frequency between 400 MHz and 900 MHz, for example.